Researchers at the University of California, Riverside, have uncovered how to manipulate electrical flow through crystalline ...

This brief presents a low-voltage D-type flip flop (D-FF) and its application in the sequential circuits, namely shift register (SR) and counter. These circuits were fabricated on a 30 μm thick ...

A 1.3–4-GHz quadrature-phase digital delay-locked loop (DDLL) with sequential delay control and a reconfigurable delay line is designed using a 28 nm CMOS process. The time resolution of the DDLL is ...

By using a new type of lacunary tungstoselenite {Se2W29O103} (1), which contains a “defect” pentagonal {W(W)4} unit, we explored the assembly of clusters using this building block and demonstrate how ...