Focusing on internal high-voltage (V/sub pp/) switching and generation for low-voltage NAND flash memories, this paper describes a V/sub (pp)/ switch, row decoder, and charge-pump circuit. The ...

The article illustrates techniques for generating parallel logic outputs with industrial serialized digital inputs.

This paper presents the design techniques of Gb/s CMOS SCL circuits. Basic SCL functional cells including a 2:1 multiplexer, a D-latch, and XOR/NXOR, AND/NAND, OR/NOR gates are described in detail.