News

IEEE5d
Low power CMOS NAND gate using DVS and mutithreshold CMOS technique
The NAND gate is designed using DVS and MTCMOS technique gives least power consumption. All the simulations have been performed on Tanner EDA Tool version 14.1.
IEEE8d
Dual-Gate Hybrid Ferroelectric Transistor Combines Photo-Switchable Logic and Memory for Encrypted Optical Communication - IEEE Xplore
In this study, we suggest a dual-gate hybrid ferroelectric transistor (DG-HFT) consisting of the vertically stacked tellurium/ α -In2Se3 junction and metal-insulator-semiconductor gate structure. This ...
C&EN22d
Transparent and Colorless Polyimides Containing Multiple Trifluoromethyl Groups as Gate Insulators for Flexible Organic Transistors with Superior Electrical Stability | ACS ...
The excellent performance of the devices with fluorinated PIs was attributed to the enhanced microstructure of the organic semiconductor and the fluorine-rich characteristic of the underlying gate ...
C&EN27d
Effects of Ti Doping on the Electrical Properties and Gate-Bias Stability of Amorphous Zinc–Tin–Oxide Thin-Film Transistors - ACS Publications
Multicationic oxide semiconductors are receiving considerable interest in electronic and optoelectronic devices owing to their tunability of physical properties by the cation compositions. Here, we ...