My guess (and I didn’t read the rest of the comments): There will be an output of 1 only if A,B,C is 1. If any of A,B or C is 0, the AND gates at the left won’t activate no matter what D does.

Figure 1 The input resistive matrix of a binary element of fractional logic.. The second node or threshold module, Figure 2, contains two comparators with a switching voltage set by resistors R1a and ...

Reversible logic contains a feature of recovering bit loss from unique input-output mapping where conventional logic has failed. Here, the reversible low power n-bit binary comparator has been ...