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IEEE2d
Qualitative Analysis of CMOS Logic Full Adder and GDI Logic Full Adder using 18 nm FinFET Technology - IEEE Xplore
In this paper we qualitatively analysed basic full adder circuitry, which is implemented using CMOS technology (28T) and GDI technique (10T) using 18nm FinFET technology. The primary objective is to ...
IEEE5d
Prefix Parallel Adder Virtual Implementation in Reversible Logic
This paper demonstrates a simplified approach for reversible logic synthesis based on direct translation of the circuit VHDL description into virtual Fredkin gates. We investigate the size and speed ...