In a hard-to-articulate way, it’s somewhat comforting to know that even in our world of highly integrated, multifunction ...

An experimental 0.6-V 57.5-fJ/conversion-step 250-kS/s 8-bit rail-to-rail successive approximation (SA) analog-to-digital converter (ADC) implemented in a standard CMOS 0.18 μm digital process is ...

A reconfigurable, highly time-interleaved ADC architecture that substantially decouples comparator requirements from input signal bandwidth and system sampling rate constraints is presented. A highly ...