A 7-bit TB ADC is implemented with a 4× folding VTC having a 2-bit digital output and a 5-bit pipelined TDC for high-speed low-power operation. A TB ADC fabricated in a 1-V 65-nm CMOS process achieves ...

A 224 Gb/s 3 pJ/bit 40 dB Insertion Loss Transceiver in 3-nm FinFET CMOS ... Published in: IEEE Journal of Solid-State Circuits ( Volume: 60 , Issue: 1 , January 2025 ) ...