Figure 2 Schematic diagram of wire break detector using CMOS memory cell (shown in broken box). If using the CD40106, only one gate is needed for the oscillator (Schmitt inputs). An additional gate ...

Similarly, when a high voltage (15V) is applied at the gate terminal, the MOSFET operates in the saturated mode, and a low impedance is present between the drain and source terminals of the MOSFET.

Therefore, by forcing input B to a logic low, Q2 is always closed and Q6 is always opened, and you can use A as input 1 and C as input 2, with the gate working as a two-input CMOS NAND gate.

The NAND gate is a circuit that outputs '0' when both inputs are '1', and '0' otherwise, so if you arrange the NAND gate as follows, the Invert circuit is completed.