A quad 2-input NAND gate is hardly the ... and 5 V TTL is compatible with both 3.3 and 5 V logic input signals because the high level threshold is around 2.7 Volts vs 3.5 V for the CMOS ...

Therefore, by forcing input B to a logic low, Q2 is always closed and Q6 is always opened, and you can use A as input 1 and C as input 2, with the gate working as a two-input CMOS NAND gate.