This metric provides an overall view of an ADC’s DC performance. Q: What about the AC performance? A: The AC performance depends on the ADC’s architecture. Common ones are the delta-sigma [1], ...

A 14-bit successive approximation analog-to-digital converter (SAR ADC) with capacitive calibration has been designed based on the SMIC. 18 μm CMOS process. The overall architecture is in fully ...

For example, assuming a 5 V reference, you will guess 2.5 V first. If the voltage is lower, your next guess will be 1.25 V. If 2.5 was the low voltage, your next guess will be 3.75 V.

A successive approximation register ADC works by quickly cycling through all possible voltage levels in its input range, eventually zeroing in on the voltage of the input signal at that moment and ...

For example, a DTMF decoder samples a telephone signal to determine which button is depressed on a touchtone keypad. Here, the concern is the measurement of a signal's power (at a given set of ...

This paper presents a 10 bit successive approximation ADC in 65 nm CMOS that benefits from technology scaling. It meets extremely low power requirements by using a charge-redistribution DAC that uses ...

Incremental zoom ADCs can be made in CMOS and are showing up in IoT sensing applications where high-resolution and accuracy has to be combined with low-power operation from low-voltage rails. In a ...

The Successive Approximation ADC is the ADC of choice for low-cost medium to high-resolution applications, the resolution for SAR ADCs ranges from 8 - 18 bits, with sample speeds up to 5 mega-samples ...

Massive deployment of wireless autonomous sensor nodes requires their lifetime extension and cost reduction. The analog frontend (AFE) plays a key role in this context. This paper presents a ...