Abstract: This paper presents the JAFARDD (a Java Architecture based on a Folding Algorithm, with Reservation stations, Dynamic translation, and Dual processing) processor. JAFARDD dynamically ...

We present the design of a mathematical co-processor of integer arithmetic for numbers represented with 1024 bits in a FPGA. The co-processor carries out modular multiplication trough the hardware ...

Abstract: This paper proposes design of frame buffer for a digital image processor. This design is implemented on Virtex-6 Field Programmable Gate Array (FPGA). In this work, three classes of ...

we have used a data-driven self-timed architecture and a binary decision diagram, which reduce the timing design difficulty in high frequency operation. The processor, which contains 7,300 Josephson ...

Abstract: This paper presents an effective hybrid test program for the software-based self-testing (SBST) of pipeline processor cores. The test program combines a deterministically developed program ...