The multivendor UALink Consortium has defined its first low-latency, accelerator‐to‐accelerator communication specification, UALink 200G 1.0.

With 100Base-T1 and BroadR-Reach compatibility, this 1G Ethernet PHY IP is tailored to in-vehicle networking, allowing high-speed, low-latency data transmission. Leveraging 28nm technology, it ...

For exceptional flexibility and interoperability, Microchip Technology (Nasdaq: MCHP) today announces it has expanded its SPE solutions with its family of LAN887x Ethernet PHY transceivers ...

IEEE 802.3cz PMD Transmitter Conformance Figure 3 illustrates the optical physical medium dependent (PMD) transmitter conformance test block diagram, which is slightly modified from IEEE 802.3cz. 3.

Ethernet speed boost Synopsys' design supports 4 x 400G, 2 x 800G, and 1.6T Ethernet rates with 112 Gbps and 224 Gbps SerDes. The solution includes 224G Ethernet PHY and verification IP, 1.6T ...

It’s a busy company. This week, Synopsys is running out a 1.6T Ethernet IP package that includes multi-channel and multi-rate MAC and PCS Ethernet controllers that support up to 1.6 Tb/sec, 224 Gb/sec ...

Synopsys’ IP solution, including new 1.6T MAC and PCS Ethernet controllers, 224G Ethernet PHY IP, and verification IP, will help to accelerate time to market for AI and HPC networking chips. The ...

HSINCHU, Taiwan, November 16, 2023--Faraday (TWSE: 3035) announces the availability of its 4-port Gigabit Ethernet PHY on UMC's 28HPC+ process.

MaxLinear, Inc., a leader in Ethernet and network solutions, today announced the market availability of its latest generation of single-port 1 G Ethernet PHYs, complementing its already robust ...

Raspberry Pi RP1 block diagram There’s no mention of flash storage for the firmware, but Eben Upton explains the datasheet release is only partial and aimed at developers implementing drivers for the ...