CMOS downscaling poses a growing concern for circuit lifetime reliability. Bias temperature instability (BTI) is a major source of transistor aging, causing a threshold voltage increase in CMOS ...

Abstract: This brief presents a 14-bit 4 GS/s time-interleaving ADC design using two interleaved sub-ADCs. The sub-ADC achieves 2 GS/s conversion rate in 28 nm CMOS technology and uses pipelined ...