Of course, what I've just described is only one way to use the DQM, counters, extended tag RAM, and other QoS hardware in order to enforce cache usage constraints on a per-thread basis.

Memory Hierarchy Design – Part 3. Memory technology and optimizations, which examined innovations in main memory that offer improved system performance; Memory Hierarchy Design – Part 4. Virtual ...

It is, in fact, suitable for both stand-alone and embedded memories at various points in the memory hierarchy, going all the way from non-volatile DRAM to Flash-like memories.