Over on GitHub, [ttsiodras] wanted to learn VHDL. So he started with an algorithm to do Mandelbrot sets and moved it to an FPGA. Because of the speed, he was able to accomplish real-time zooming.

You will learn the history of both VHDL and Verilog and how to use them for design entry and verification with FPGAs and ASICs. You will use current HDL software tools for FPGA development, and ...

Very cool! Verilog and VHDL are kind of like the C and ADA of the FPGA world. Verilog will seem familiar to you if you’re used to writing code for computers. For instance, it will turn integer ...